1. Field of the Invention
The present invention relates to a digital-to-analog converter (DAC) and a level shifter of the DAC thereof, and more particularly to a DAC having a low swing level shifter and the low swing level shifter thereof.
2. Description of the Prior Art
Digital-to-analog converters are used to transfer the digital input signals into analog output signals and are essential in many systems, such as video systems, audio systems, wired communication systems, and wireless communication systems.
There have been many various DAC structures that have applied in many different fields. In high-speed and high-resolution applications, i.e. the data length is greater than 10 bits and the sampling frequency is greater than 1000 Mz, the current-mode DAC structure is a popular choice to convert digital signals into analog signals because it can directly drive resistive load and do not need any output voltage buffer. The current-mode DAC is composed of many current cells, and the finite output impendence of the current cell of the DAC is a key factor to affect the performance of the DAC. The output impendence of the current cell must be high enough to avoid ruining the performance of the DAC.
Please refer to FIGS. 1–2. FIG. 1 is a functional diagram of a current-mode DAC 10 according to the prior art. FIG. 2 is a schematic diagram of a current cell 14 used in the current-mode DAC 10. The current-mode DAC 10 comprises two thermometer decoders 11, 12 and a plurality of current cells 14. The two thermometer decoders 11 and 12 are used to decode the six binary signals B1, B2, B3, B5, B6, and B7 and then to generate and transmit corresponding binary signals, such as the input signals in1, in2, and in3 shown in FIG. 2, to the current cells 14. Each of the current cells 14 can be separated into a core voltage part 16 and an IO voltage part 18. The working voltage of the core voltage part 16 is less than the working voltage of the IO voltage part 18. A local decoder 20 decodes the received binary input signals in1–in3 to control the output of the current cell 14. A clock circuit 22 and a latch circuit 24 are connected between the local decoder 20 and a level shifter 26 of the current cell 14. The level shifter 26 is used to convert a first input signal INP into a second output signal OUTN and to convert a second input signal INN into a first output signal OUTP. A current source 27 outputs corresponding current according the output signals OUTN and OUTP of the level shifter 26. The current source 27 has four PMOS transistors T1, T2, T3, and T4. The PMOS transistors T1 and T2 are cascaded and connected to a first power terminal VDD. The gate of the PMOS transistor T3 receives the second output signal OUTN, and the gate of the PMOS transistor T4 receives the first output signal OUTP. Only one of the two PMOS transistors T3 and T4 is turned on at a time so that the current path of the generated current of the current source 27 is controlled. For example, if the first output signal OUTP is high and the second output signal OUTN is low, the PMOS transistor T3 is turned on and the PMOS transistor T4 is turned off, and then the generated current of the current source 27 flows from the first power terminal VDD through the PMOS transistors T1, T2, and T3 to a second power terminal Vss. In addition, the working voltage of the IO voltage part 18 is applied to the first power terminal, and the second power terminal Vss is grounding. Therefore, the voltage level of the first power terminal VDD is greater than the voltage level of the second power terminal Vss.
Please refer to FIGS. 3–4. FIG. 3 is a circuit diagram of the level shifter 26 and the latch circuit 24 shown in FIG. 2, and FIG. 4 is a timing diagram of the two output signals OUTN and OUTP of the level shifter 26. The level shifter 26 has a first module 40 and a second module 42, and the latch circuit 24 has a first inverter 32 and a second inverter 34. The first module 40 of the level shifter 26 is used to convert the first input signal INP into the second output signal OUTN and comprises a NMOS transistor 28, an inverter 36, and a first output unit 44. Similarly, the second module 42 of the level shifter 26 is used to convert the second input signal INN into the first output signal OUTP and comprises a NMOS transistor 30, an inverter 38, and a second output unit 46. The first output unit 44 is an inverter and has a first PMOS transistor 47 and a first NMOS transistor 48. The second output unit 46 is also an inverter and has a second PMOS transistor 49 and a second NMOS transistor 50. The first PMOS transistor 47 and the second PMOS transistor 49 are connected to the first power terminal VDD, and the first NMOS transistor 48 and the second NMOS transistor 50 are connected to the second power terminal Vss. Therefore, the voltage gap between the first output signal OUTP and the second output signal OUTN is equal to the working voltage of the IO voltage part 18, i.e. the voltage gap between the first power terminal VDD and the second power terminal Vss, e.g. 2.5 voltages.
It is noted that the first input signal INP and the second input signal INN are complementary signals, and the first output signal OUTP and the second output signal OUTN are complementary signals. The voltage gap between the first input signal INP and the second input signal INN is equal to the working voltage of the core voltage part 16, e.g. 1.2 voltages. If the first signal INP is high and the second input signal INN is low, then the first output signal OUTP is high and the second output signal OUTN is low. Oppositely, if the first signal INP is low and the second input signal INN is high, then the first output signal OUTP is low and the second output signal OUTN is high.
Please refer to FIG. 2 and FIG. 4. Because when the PMOS transistor T3 is turned on and the PMOS transistor T4 is turned off, the voltage level of the first output signal OUTP is equal to VDD and the voltage level of the second output signal OUTN is equal to Vss. Therefore, in such case, the PMOS transistor T3 operates in a linear region. Similarly, when the PMOS transistor T3 is turned off and the PMOS transistor T4 is turned on, the voltage level of the first output signal OUTP is equal to Vss and the voltage level of the second output signal OUTN is equal to VDD. Therefore, in this case, the PMOS transistor T4 operates in a linear region. Hence, the output impendence of the current cell 14 is not greater enough to reduce the clock feedthrough effect and the glitch energy.